It is well known in the art to provide a general purpose processor that is coupled to a special purpose processor through a dual ported read/write (R/W) memory. During the operation of such a system the general purpose processor loads the memory with data to be operated on by the special purpose processor, which then operates on the data independently of the special purpose processor. When the special purpose processor finishes, the general purpose processor is enabled to retrieve the processed data from the memory. The memory may be referred to as a scratchpad memory, and the special purpose processor may be optimized for performing vector operations, matrix operations, or any other processing task that would not be efficiently performed by the general purpose processor.
In some such systems the general purpose processor may be responsible for executing a plurality of tasks or threads in a time multiplexed or other fashion, which gives the external appearance that a plurality of such threads are being executed concurrently. In this case both the general purpose processor and the special purpose processor must be capable of switching between the execution of various tasks or threads. This implies that the scratchpad memory should be managed in such a manner that the switching between tasks or threads occurs in efficient manner.
In conventional systems it is often the case that when the special purpose processor is required to switch from executing one thread to executing another thread (typically referred to as a context switch), the complete processing state of the special purpose processor must be saved. This includes the register state of the special purpose processor, as well as data stored in the scratchpad memory. While registers in the special purpose processor may be saved in a relatively short period of time, it may require an appreciable amount of time to save or swap-out the content of the scratchpad memory. A like amount of time may then be required to subsequently restore or swap-in the content of the scratchpad memory when the previously operating thread is restarted.
While in some situations it is essential that the scratchpad memory be swapped-out during a context switch, the inventor has realized that in other situations it is not essential or required. However, in conventional system the memory swapping-out operation is still performed, leading to inefficiencies in the operation of the system.
U.S. Pat. No. 5,008,812 to Bhandarkar et al. describes a method for saving the state information of a vector processor only if a new process attempts to execute a vector instruction, i.e., is about to change the current state of the vector processor. However, this patent does not suggest the application of this technique to resources other than the vector processor registers.
U.S. Pat. No. 5,428,779 to Allegrucci et al. describes a method for saving and restoring the context (state) of processors in a multi-processor system by storing code snippets that save the state to memory and restore it from memory.
U.S. Pat. No. 4,740,893 to Buchholz et al. describes the use of flags to indicate whether vector registers in a vector processor are either all zero or have changed since the last restore operation for a given vector register. The use of such `dirty bits` is said to reduce the time required to store data.
U.S. Pat. No. 5,361,337 to Okin describes the use of shadow registers in a processor to quickly switch to another process if the active process encounters a cache miss. The process switch is accomplished by selecting another register set amongst the shadow registers.
U.S. Pat. No. 5,490,272 to Mathis et al. describes a method for subdividing a time-slice allocated to a thread into finer units, so called threadlets, that can be scheduled within a time-slice. Transition between threadlets occurs at points in the application where no state needs to be saved or restored. Such points are identified in the application by special instructions.
U.S. Pat. No. 5,493,668 to Elko et al. describes a mechanism to ensure data coherency between data stored in primary memory, e.g., a cache, and secondary memory. Data is shared between processors in a multiprocessor system and each processor can change the shared data. The patent describes changes to data are preserved if those changes occur during a write-back operation to disk.
U.S. Pat. No. 5,553,305 to Gregor et al. describes the scheduling and synchronization of threads by tracking whether data are available that are required for executing a thread. The particular technique described by the patent places a thread identification into memory location where the data is expected to be found. Once the data are retrieved, the thread identification is replaced and the thread is entered into a scheduling queue.